1. Field of the Invention
The present invention relates generally to fabricating micromechanical semiconductor devices, and particularly to MEMS/NEMS devices using standard CMOS fabrication processes.
2. Technical Background
The performance of radio frequency (RF), wireless, signal processing and other such electronic systems depends in part on the accuracy and stability of the reference clock signals employed in the aforementioned systems. System clock and timing signals are typically derived from a reference clock signal that is generated by a reference oscillator. The key component of an oscillator is a device known as a resonator. As the name suggests, the device resonates in response to an input stimulus and provides a reference frequency signal corresponding to the resonant frequency. Many of state-of-the-art oscillators employ quartz resonators.
On the other hand, resonators based on MEMS technology are currently being investigated for the next generation of system applications because of the inadequacies associated with quartz resonators. Some of the characteristics that designers desire in resonators and reference oscillators include high frequency, high quality factor (Q), a small physical footprint, minimal power consumption, a wide tuning range, and low phase noise. Further, the ability to monolithically integrate MEMS/NEMS mechanical resonators, transducers and the like within conventional CMOS circuitry is highly desirable.
Until recently, designers have considered three general approaches for integrating MEMS devices and CMOS circuits. The first approach is referred to herein as “pre-MEMS” and employs a standard MEMS fabrication sequence first and follows with a CMOS transistor fabrication process. The second method is essentially the reverse of the first approach and is referred to herein as “post-MEMS.” The CMOS transistor fabrication process is performed and the MEMS device fabrication sequence follows thereafter. Essentially, the drawback associated with each of these approaches is that they require two foundry sequences to complete the device fabrication. The negative cost implications are obvious.
The third approach under consideration is referred to herein as “MEMS-in-the middle” because one or more MEMS process steps are performed in the middle of the CMOS transistor fabrication process. In other words, the CMOS fabrication process is customized to include process steps for fabricating the MEMS devices. One drawback to this approach is that the standard CMOS foundry process must be modified to include non-standard MEMS process sequences. This may require a significant re-tooling and/or modification of the CMOS foundry and directly translates to higher costs. The costs may be prohibitive because a given CMOS foundry may be unwilling to make the modifications in light of their obligations to their customer base. The disruptions to the foundry's work flow may not be worth the trouble.
In the methods described above, the integration of MEMS/NEMS devices and CMOS circuits has not been effectively realized because of incompatibilities with MEMS/NEMS processes and standardized CMOS foundry processes. At this point, it may be helpful to the reader to explain what the term “standard CMOS foundry process” means. A standard CMOS process refers to a predefined sequence of “unit processes” required to fabricate a CMOS integrated circuit. Each unit process may include several fabrication steps. A series of unit processes may be employed as an “integration module” to obtain a desired circuit feature. For example, a transistor gate structure may be fabricated using a predefined “gate module.” The overall CMOS process, therefore, includes a defined sequence of integrated modules that may be specified using a “layer map.” Accordingly, CMOS foundries offer standard CMOS fabrication processes that are specified using predefined, layer maps to accommodate the needs of most of its customers.
By way of example, MOSIS is a low-cost prototyping and small-volume production service for VLSI circuit development. It provides its customers with layer maps that include a well defined set of rules and options that must be followed when submitting a design. MOSIS provides a document that defines the official MOSIS scalable CMOS (SCMOS) layout rules. The user will provide the MOSIS fabrication facility with a design specification in accordance with the map. The SCMOS Layer map is reproduced in Table I as an example of a “standard CMOS foundry process.” Table I illustrates the standardized layer map that defines the CMOS process integration flow.
TABLE IExample SCMOS Layer MapRuleLayerSectionNotesN WELL1P WELL1SCPxxCAP WELL17, 18SCN3MLCACTIVE2THICK ACTIVE24SCN4M (TSMC only), SCN4ME, SCN5M, SCN6MPBASE16SCNAPOLY CAP123SCNPCPOLY3SILICIDE BLOCK20SCN3M, SCN4M (TSMC only), SCN5M, SCN6MN PLUS SELECT4P PLUS SELECT4POLY211, 12, 13SCNE, SCNA, SCN3ME, SCN4MEHI RES IMPLANT27SCN3MECONTACT5, 6, 13POLY CONTACT5Can be replaced by CONTACTACTIVE CONTACT6Can be replaced by CONTACTPOLY2 CONTACT13SCNE, SCNA, SCN3ME, SCN4ME Can be replaced by CONTACT.METAL17VIA8METAL29VIA214SCN3M, SCN3ME, SCN3MLC, SCN4M, SCN4ME, SCN5M, SCN6MMETAL315SCN3M, SCN3ME, SCN3MLC, SCN4M, SCN4ME, SCN5M, SCN6MVIA321SCN4M, SCN4ME, SCN5M, SCN6MMETAL422SCN4M, SCN4ME, SCN5M, SCN6MCAP TOP METAL28SCN5M. SCN6MVIA425SCN5M, SCN6MMETAL526SCN5M, SCN6MVIA529SCN6MMETAL630SCN6MDEEP N WELL31SCN5M, SCN6MGLASS10PADSOptional non-fab layer used solely to highlight the bonding pads.
Each layer depicted above has associated with it predefined rules (column two) and technology codes (column three). Essentially, the layer map specifies the film stack for the CMOS circuit. Those of ordinary skill in the art will understand that there are other standard foundry CMOS processes including the Austriamicrosystems, IBM, TSMC fabrication processes, etc.
Recently, an approach for integrating MEMS/NEMS devices and CMOS circuits using standard CMOS fabrication processes has been under consideration. In this approach, certain MEMS structures such as bridges and cantilevers may be fabricated using a standard CMOS foundry process. However, the bridge and cantilever structures that may be fabricated by the contemplated method are very small. In one design currently under consideration, portions of the bridge on either side of the transverse bridge center-line are removed such that the capacitive detection plates are formed by the cross-sectional edges of the bridge along the cut-lines bisecting the bridge in the transverse direction. The drawbacks associated with this proposed method are that the capacitor pick-up surfaces are disposed “in-plane.” Another drawback relates to the fact that the surface area for capacitive pick-up is on the order of about 1 μm2. The transverse cut-lines described above must be relatively small to obtain the required gap for the capacitive detector. In fact, the size of the detector gap becomes a function of the linewidth of the illumination source in the photolithographic process. As the linewidth becomes smaller, more sophisticated (and hence, more expensive) illumination assemblies are required. Another drawback of the standard CMOS process under consideration relates to the fabrication of a MEMS device and its subsequent release. The MEMS device would be fabricated such that there is very little internal stress in the device such that its rigidity is relatively low. After the device is fabricated using the standard foundry process, the MEMS device would be exposed to gain access thereto. At this point, the region under the bridge span would be filled with an oxide material that must be removed by wet-etching. Unfortunately, when the etchant evaporates, it has a tendency to introduce a suction force such that the bridge is forced downwardly and sticks to the underlying substrate. When this occurs in any MEMS release process, the device does not release. This phenomenon is known as stiction. Accordingly, MEMS devices that may be fabricated using this technique would have a very low yield rate.
As noted above, stiction is often an issue in standard MEMS devices (i.e., those devices fabricated using standard non-CMOS techniques). In order to solve the stiction problem, those of ordinary skill in the art often resort to what is known as a “critical point dry” technique whereby liquid carbon-dioxide is introduced to replace the wet etchant before evaporation occurs. Subsequently, the liquid carbon-dioxide reverts to its gaseous state such that the stiction forces are not introduced. While this additional step may be used to improve the yield of the standard CMOS approach currently under consideration, it has several drawbacks. First, it is relatively expensive. Second, it introduces additional non-CMOS steps into the back end of the process. Accordingly, it defeats the very purpose of using a standard CMOS foundry process to produce MEMS devices; i.e., to avoid expensive post fabrication processing.
What is needed, therefore, is an improved method for integrating MEMS/NEMS devices and CMOS circuits using a standard CMOS foundry process. An improved process is needed such that the MEMS devices are characterized by improved actuation and detection capabilities, lower power consumption, and a greater yield, without the need for post fabrication stiction-inhibiting processes.